The present invention relates in general to the field of integrated circuits and similar technologies, and in particular to built-in self testing of integrated circuits and similar technologies.
Traditional methods of testing semiconductor devices are quickly becoming obsolete. The use of functional patterns derived for design verification as manufacturing test patterns is becoming increasingly unacceptable. Some of the most severe problems associated with this approach are high test development times, defect coverages that are low or hard to measure, and poor diagnosability. Therefore test techniques were developed which based analysis on the design structure rather than on functionality.
The largest problem with both the functional and design structure based test techniques is their reliance on the use of automatic test equipment (ATE) to apply the test patterns to the device's external inputs and measure responses on the device's external outputs. This approach does not provide a means to adequately detect all of the device's internal defects. Direct access to the internal structures of a device is necessary. This requirement has led to the development of design-for-test (DFT) and built-in self-test (BIST) techniques and methods.
DFT techniques consist of design rules and constraints aimed at increasing the testability of a design through increased internal controllability and observability. The most popular form of DFT is scan design, which involves modifying all internal storage elements such that in test mode they form individual stages of a shift register for scanning in test data stimuli and scanning out test responses.
Conceptually, the BIST approach is very simple. It is based on the realization that much of a circuit tester's electronics is semiconductor-based, just like the products it is testing, and that the challenge in ATE design, and many of the emerging limitations in ATE-based testing, lie in the interface to the device under test. In light of this fact, the BIST approach can be described as an attempt to move many of the already semiconductor-based test equipment functions into the products under test and eliminate the complex interfacing. This embedding of functionality has many benefits.
Logic built-in self-test (LBIST) is used for manufacturing test at all package levels and for system self-test. The basic idea in LBIST is to add a pseudorandom-pattern generator (PRPG) to the inputs and a multiple-input shift register (MISR) to the outputs of the device's internal storage elements, which are arranged to form scan chains known as LBIST channels. An LBIST controller generates all necessary waveforms for repeatedly loading pseudorandom patterns into the scan chains, initiating a functional cycle, and logging the captured responses out into the MISR. The MISR compresses the accumulated responses into a code known as a signature. Any corruption in the final signature at the end of the test indicates a defect in the chip.
System LBIST operation has historically been one of the highest power drain events in the operation of a microchip. This is primarily due to the high number of latches that are switching during the scan operations. Solutions in the past have included slowing the speed of the scans and/or staggering the scan clocks. Other solutions have included partitioning the design into LBIST islands and scanning only those islands during reduced partition tests. Drawbacks to these solutions involve longer test time—either by extending the scan time, or by requiring numerous tests that overlap tested islands to maintain coverage. This partitioning solution also requires costly extra design effort that is unique to each chip design and not repeatable from chip to chip.